A vertical trench MOS gate-type semiconductor element has been proposed in which a gate region is provided in a trench in order to reduce the on resistance of a MOS-type semiconductor element with a small area. FIG. 3 is a cross-sectional view illustrating a main portion of a general vertical trench gate MOS-type semiconductor element and a junction edge termination region thereof. In the semiconductor element illustrated in FIG. 3, the breakdown voltage of a junction edge termination region 69 needs to be higher than that of an active region 68 such that a current caused by avalanche breakdown flows to the active region 68.
Therefore, a p− diffusion region 54 with a concentration lower than that of a p-type base region 55 is provided in the junction edge termination region 69. In this way, a depletion layer is likely to be extended from the active region 68 to the junction edge termination region 69 when an off voltage is applied. Therefore, the maximum field intensity of the junction edge termination region 69 is sufficiently reduced and the breakdown voltage of the junction edge termination region 69 increases. As a result, the overall breakdown voltage of the trench gate MOS-type semiconductor element is determined by the p-type base region junction or breakdown due to the concentration of the electric field on the bottom of the trench gate.
Further, a complex semiconductor device which is called an insulated gate semiconductor device with a protection function in which the lateral semiconductor element for protection illustrated in the cross-sectional view of FIG. 2 is formed on the same semiconductor substrate has been proposed in order to improve the breakdown voltage reliability or breakdown resistance of the trench gate MOS-type semiconductor element illustrated in FIG. 3 serving as an output-stage element at a low cost (Patent Literature 1).
FIG. 2 is a cross-sectional view illustrating a general lateral planar MOS-type semiconductor element for control. The protective semiconductor element illustrated in FIG. 2 includes a lateral n-channel MOSFET which is provided in a p well diffusion region 35 partitioned by a well junction 40.
In a complex semiconductor device of the semiconductor elements illustrated in FIGS. 2 and 3, a common semiconductor substrate including an n+ substrate (corresponding to reference numeral 32 in FIG. 2 and reference numeral 52 in FIG. 3) and an n− epitaxial layer (corresponding to reference numeral 33 in FIG. 2 and reference numeral 53 in FIG. 3) provided on the n+ substrate includes active regions (corresponding to reference numeral 48 in FIG. 2 and reference numeral 68 in FIG. 3) of a protective lateral semiconductor element and a vertical MOSFET (MOS field effect transistor) and junction edge termination regions (corresponding to reference numeral 49 in FIG. 2 and reference numeral 69 in FIG. 3) which surround the active regions.
In the complex semiconductor device, the off voltage applied to the vertical MOSFET, which is an output-stage element, is applied to the output-stage element and the well junction 40 of the protective semiconductor element illustrated in FIG. 2 at the same time. Therefore, both the active region 68 of the vertical MOSFET illustrated in FIG. 3 and the well junction 40 (that is, the pn junction between the p− well diffusion region 35 and the n− epitaxial layer 33) of the protective semiconductor element illustrated in FIG. 2 need to have an effective breakdown voltage for the off voltage.
In the protective semiconductor element illustrated in FIG. 2, the lateral n-channel MOSFET is formed in the well diffusion region partitioned by the well junction 40. The breakdown voltage of the well junction 40 is, for example, 50 V. Further, in the following description, for convenience, a breakdown voltage of 50 V or less is referred to as a low breakdown voltage and a breakdown voltage higher than 50 V is referred to as a high breakdown voltage.
The active region 48 of the protective semiconductor element illustrated in FIG. 2 includes a gate oxide layer 37, a gate electrode 36, a drain region 38a, a source region 38b, a p-type base region and a base contact region 39 which form a portion of a p− well diffusion region 35, and a drain electrode 12, a source electrode 13, and a base electrode 14 which come into contact with the surface of each region. In addition, the junction edge termination region 49 includes a LOCOS oxide layer 41 in order to prevent a reduction in the breakdown voltage of the well junction 40.
On the other hand, the vertical trench MOS gate-type semiconductor element portion illustrated in FIG. 3 includes a source electrode 65 that is connected to an n+ source region 58, a p-type base region 55, and a p+ contact region 60 provided above the main surface of the semiconductor substrate and a drain electrode 51 that comes into contact with the n+ substrate 52 in the drain region on the rear side. The gate electrode 56 is formed by filling polysilicon in the trench with a gate oxide layer 57 interposed therebetween and is connected to a gate electrode pad on the surface of the substrate by a gate electrode line (not illustrated). A structure including, for example, the p-type base region 55, the gate electrode 56, the gate oxide layer 57, the n+ source region 58, and the p+ contact region 60 with high impurity concentration as described above is referred to as a trench MOS gate structure.
The junction edge termination region 69 surrounding the active region 68 includes a LOCOS oxide layer 61 and a p− diffusion region 54 having an electric field reducing function and is provided such that the breakdown voltage thereof is higher than that of the main junction between the p-type base region 55 and the n− epitaxial layer 53. In the junction edge termination region 69, since the junction is not flat, the maximum field intensity generated by the application of the off voltage is likely to be concentrated on a narrow region and an element breakdown is likely to occur. Therefore, the p− diffusion region 54 with an electric field reducing function is needed in order to prevent the concentration of the current due to a reduction in the breakdown voltage.
In the vertical trench gate MOSFET element illustrated in FIG. 3, the trench gate structure makes it possible to improve channel density and reduce the off resistance, as compared to the planar gate MOSFET. Therefore, the trench gate structure is applied to a power IC which includes the vertical MOSFET and has a rated voltage of about 50 V to 100 V or a high breakdown voltage glass higher than the rated voltage.
As such, when the breakdown voltage is increased to 50 V or more, the electric field is not sufficiently reduced in the depletion layer which is extended when the off voltage is applied, in the junction edge termination region including only the LOCOS oxide layer 61 and the breakdown voltage is likely to be reduced in the junction edge termination region. Therefore, the p− diffusion region 54 described above is provided in addition to the LOCOS oxide layer 61, which makes it possible to reduce the electric field and prevent a reduction in the breakdown voltage.
FIG. 5 is a cross-sectional view illustrating a main portion of the vertical trench gate MOS-type semiconductor element according to the related art and the junction edge termination region thereof. FIG. 5 illustrates a preferred example for the vertical trench gate MOS-type semiconductor element with a high breakdown voltage. As illustrated in FIG. 5, an element has been proposed which does not include the above-mentioned protective semiconductor element and includes an active region 68 having a vertical trench gate MOS structure and a junction edge termination region 69 which is arranged so as to surround the outer circumference of the active region 68 and includes a p− RESURF (Reduced surface electric field) region 70 for reducing the electric field (for example, see the following Patent Literature 2). A field plate 56c may be formed on an oxide layer 61 and the RESURF region 70.
In a complex semiconductor device, such as a trench gate-type power IC formed by integrating the protective semiconductor element with the vertical trench gate MOS-type semiconductor element, for the same reason as described above, the junction edge termination region 69 needs to be configured such that the breakdown voltage thereof is higher than a main junction breakdown voltage in order to reduce the off resistance of the vertical trench gate MOS-type semiconductor element and prevent a reduction in the breakdown voltage. In order to meet the requirements, it is effective to add an electric field reducing mechanism, such as a polysilicon film field plate 67 or a metal film field plate 66, to the junction edge termination region 69, in addition to the same region as the p− diffusion region 54 illustrated in FIG. 3. In addition, in Patent Literature 2 relating to the above-mentioned trench gate-type power IC, a region corresponding to the p− RESURF region 70 which is provided in order to reduce the electric field in the junction edge termination region is a region having the known RESURF effect, that is, a region having the effect of reducing field intensity by sufficiently depleting substantially the entire p− RESURF region 70 such that the surface thereof is not fully depleted.